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BCSHCI
2009
15 years 7 months ago
Evolving and augmenting worth mapping for family archives
We describe the process of developing worth maps from field research and initial design sketches for a digital Family Archive, which resulted in a more simple and flexible worth m...
Gilbert Cockton, David S. Kirk, Abigail Sellen, Ri...
ISPD
1997
ACM
142views Hardware» more  ISPD 1997»
15 years 11 months ago
Minimization of chip size and power consumption of high-speed VLSI buffers
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
D. Zhou, X. Y. Liu
ESCIENCE
2007
IEEE
16 years 1 months ago
Towards a Grid-Enabled Simulation Framework for Nano-CMOS Electronics
The electronics design industry is facing major challenges as transistors continue to decrease in size. The next generation of devices will be so small that the position of indivi...
Liangxiu Han, Asen Asenov, Dave Berry, Campbell Mi...
FPL
2003
Springer
259views Hardware» more  FPL 2003»
15 years 12 months ago
Branch Optimisation Techniques for Hardware Compilation
Abstract. This paper explores using information about program branch probabilities to optimise reconfigurable designs. The basic premise is to promote utilization by dedicating mo...
Henry Styles, Wayne Luk
CODES
1999
IEEE
15 years 11 months ago
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling
In this paper, we propose a fast and simple heuristic for the cosynthesis problem targeting the system-on-chip (SOC) design. The proposed algorithm covers from implementation sele...
Hyunok Oh, Soonhoi Ha