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DFT
2006
IEEE
105views VLSI» more  DFT 2006»
16 years 19 days ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
HICSS
1995
IEEE
128views Biometrics» more  HICSS 1995»
15 years 10 months ago
Instruction Level Parallelism
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
BMCBI
2007
147views more  BMCBI 2007»
15 years 6 months ago
Hon-yaku: a biology-driven Bayesian methodology for identifying translation initiation sites in prokaryotes
Background: Computational prediction methods are currently used to identify genes in prokaryote genomes. However, identification of the correct translation initiation sites remain...
Yuko Makita, Michiel J. L. de Hoon, Antoine Danchi...
ICCAD
2009
IEEE
147views Hardware» more  ICCAD 2009»
15 years 4 months ago
SAT-based protein design
Computational protein design can be formulated as an optimization problem, where the objective is to identify the sequence of amino acids that minimizes the energy of a given prot...
Noah Ollikainen, Ellen Sentovich, Carlos Coelho, A...
ICRA
2003
IEEE
178views Robotics» more  ICRA 2003»
15 years 12 months ago
Design of six sigma supply chains
Abstract—Variability reduction and business process synchronization are acknowledged as key to achieving sharp and timely deliveries in supply chain networks. In this paper, we i...
Dinesh Garg, Yadati Narahari, Nukala Viswanadham