Sciweavers

3192 search results - page 254 / 639
» The minimum latency problem
Sort
View
ASAP
2000
IEEE
142views Hardware» more  ASAP 2000»
15 years 11 months ago
Contention-Conscious Transaction Ordering in Embedded Multiprocessors
This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digi...
Mukul Khandelia, Shuvra S. Bhattacharyya
DATE
2000
IEEE
83views Hardware» more  DATE 2000»
15 years 11 months ago
Wave Steered FSMs
In this paper we address the problem of designing very high throughput finite state machines (FSMs). The presence of loops in sequential circuits prevents a straightforward and g...
Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-...
ASPDAC
2005
ACM
132views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Automatic synthesis and scheduling of multirate DSP algorithms
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...
VLSID
2010
IEEE
202views VLSI» more  VLSID 2010»
15 years 4 months ago
Processor Architecture Design Using 3D Integration Technology
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, is one of the promising solutions to mitigate the interconnect...
Yuan Xie
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
16 years 6 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne