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ACSD
2010
IEEE
239views Hardware» more  ACSD 2010»
15 years 4 months ago
A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...
W. B. Toms, David A. Edwards
IPPS
2010
IEEE
15 years 4 months ago
A PRAM-NUMA model of computation for addressing low-TLP workloads
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
Martti Forsell
NOCS
2010
IEEE
15 years 4 months ago
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs
The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an importan...
Chia-Hsin Owen Chen, Niket Agarwal, Tushar Krishna...
TMM
2010
102views Management» more  TMM 2010»
15 years 1 months ago
A Real-Time Framework for Video Time and Pitch Scale Modification
A framework is presented which addresses the issues related to the real-time implementation of synchronized video and audio time-scale and pitch-scale modification algorithms. It a...
Ivan Damnjanovic, Dan Barry, David Dorran, Joshua ...
JCB
2006
125views more  JCB 2006»
15 years 6 months ago
Hypothesis Generation in Signaling Networks
Biological signaling networks comprise the chemical processes by which cells detect and respond to changes in their environment. Such networks have been implicated in the regulati...
Derek A. Ruths, Luay Nakhleh, M. Sriram Iyengar, S...