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JDA
2006
83views more  JDA 2006»
15 years 6 months ago
Partitioning a graph of bounded tree-width to connected subgraphs of almost uniform size
Assume that each vertex of a graph G is assigned a nonnegative integer weight and that l and u are nonnegative integers. One wishes to partition G into connected components by del...
Takehiro Ito, Xiao Zhou, Takao Nishizeki
APPROX
2008
Springer
173views Algorithms» more  APPROX 2008»
15 years 8 months ago
Connected Vertex Covers in Dense Graphs
We consider the variant of the minimum vertex cover problem in which we require that the cover induces a connected subgraph. We give new approximation results for this problem in d...
Jean Cardinal, Eythan Levy
DAC
1994
ACM
15 years 10 months ago
RC Interconnect Optimization Under the Elmore Delay Model
An e cient solution to the wire sizing problem WSP usingthe Elmoredelaymodelisproposed. Two formulations of the problem are put forth: in the rst, the minimum interconnect delay i...
Sachin S. Sapatnekar
ISCAS
2005
IEEE
158views Hardware» more  ISCAS 2005»
15 years 12 months ago
Designing optimized pipelined global interconnects: algorithms and methodology impact
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
Vidyasagar Nookala, Sachin S. Sapatnekar
ISSS
2000
IEEE
109views Hardware» more  ISSS 2000»
15 years 9 months ago
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors
The paper presents a novel software-pipelining algorithm suitable for optimizing compilers targeting embedded VLIW processors. The proposed algorithm is different from previous ap...
Cagdas Akturan, Margarida F. Jacome