2605 search results - page 458 / 521 » The many levels of CSCL |
184
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ISCA
2002
IEEE
15 years 11 months ago
2002
IEEE
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
326
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SIGMOD
2010
ACM
15 years 11 months ago
2010
ACM
Many modern enterprises are collecting data at the most detailed level possible, creating data repositories ranging from terabytes to petabytes in size. The ability to apply sophi...
187
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SPAA
2010
ACM
15 years 11 months ago
2010
ACM
Transactional Memory (TM) is a promising technique that simplifies parallel programming for shared-memory applications. To date, most TM systems have been designed to efficientl...
179
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IWMM
2010
Springer
15 years 11 months ago
2010
Springer
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
165
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SBCCI
2009
ACM
15 years 11 months ago
2009
ACM
The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applicat...