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SAMOS
2004
Springer
15 years 11 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
ISCA
2003
IEEE
120views Hardware» more  ISCA 2003»
15 years 11 months ago
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes
While removing software bugs consumes vast amounts of human time, hardware support for debugging in modern computers remains rudimentary. Fortunately, we show that mechanisms for ...
Milos Prvulovic, Josep Torrellas
SEMWEB
2001
Springer
15 years 10 months ago
OntoMap - the Guide to the Upper-Level
Abstract. The upper-level ontologies are theories that capture the most common concepts, which are relevant for many of the tasks involving knowledge extraction, representation, an...
Atanas K. Kirakov, Marin Dimitrov
SIGLEX
1991
15 years 9 months ago
Aspectual Requirements of Temporal Connectives: Evidence for a Two-Level Approach to Semantics
This paper argues for a two-level theory of semantics as opposed to a one-level theory, based on the example of the system of temporal and durationM connectives. Instead of identi...
Michael Herweg
BMCBI
2010
100views more  BMCBI 2010»
15 years 6 months ago
A robust method for estimating gene expression states using Affymetrix microarray probe level data
Background: Microarray technology is a high-throughput method for measuring the expression levels of thousand of genes simultaneously. The observed intensities combine a non-speci...
Megu Ohtaki, Keiko Otani, Keiko Hiyama, Naomi Kame...