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» The many levels of CSCL
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ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
16 years 1 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
VEE
2009
ACM
240views Virtualization» more  VEE 2009»
16 years 1 months ago
Memory buddies: exploiting page sharing for smart colocation in virtualized data centers
Many data center virtualization solutions, such as VMware ESX, employ content-based page sharing to consolidate the resources of multiple servers. Page sharing identifies virtual...
Timothy Wood, Gabriel Tarasuk-Levin, Prashant J. S...
ICIAR
2009
Springer
16 years 29 days ago
Implicit Active-Contouring with MRF
In this paper, we present a new image segmentation method based on energy minimization for iteratively evolving an implicit active contour. Methods for active contour evolution is ...
Pierre-Marc Jodoin, Venkatesh Saligrama, Janusz Ko...
IMC
2009
ACM
16 years 28 days ago
Characterizing VLAN-induced sharing in a campus network
Many enterprise, campus, and data-center networks have complex layer-2 virtual LANs (“VLANs”) below the IP layer. The interaction between layer-2 and IP topologies in these VL...
Muhammad Mukarram Bin Tariq, Ahmed Mansy, Nick Fea...
DSRT
2008
IEEE
16 years 26 days ago
Interfacing and Coordination for a DEVS Simulation Protocol Standard
The DEVS formalism has been adopted and developed independently by many research teams, which led to various DEVS implementation versions. Consequently, different DEVS implementat...
Khaldoon Al-Zoubi, Gabriel A. Wainer