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» The many levels of CSCL
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IWPC
2003
IEEE
15 years 11 months ago
Design Recovery of a Two Level System
Many applications have one or more important modules that are written in a language other than conventional procedural or object oriented languages. These languages are often tran...
Thomas R. Dean, Yuling Chen
CHARME
2003
Springer
97views Hardware» more  CHARME 2003»
15 years 11 months ago
Convergence Testing in Term-Level Bounded Model Checking
We consider the problem of bounded model checking of systems expressed in a decidable fragment of first-order logic. While model checking is not guaranteed to terminate for an ar...
Randal E. Bryant, Shuvendu K. Lahiri, Sanjit A. Se...
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
15 years 11 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
WCRE
2002
IEEE
15 years 11 months ago
Exposing Data-Level Parallelism in Sequential Image Processing Algorithms
As new computer architectures are developed to exploit large-scale data-level parallelism, techniques are needed to retarget legacy sequential code to these platforms. Sequential ...
Lewis B. Baumstark Jr., Linda M. Wills
ICPP
1999
IEEE
15 years 10 months ago
Trace-Level Reuse
Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, th...
Antonio González, Jordi Tubella, Carlos Mol...