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CODES
2003
IEEE
15 years 12 months ago
A fast parallel reed-solomon decoder on a reconfigurable architecture
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
DATE
2003
IEEE
97views Hardware» more  DATE 2003»
15 years 12 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
DISCEX
2003
IEEE
15 years 12 months ago
DynaBone: Dynamic Defense Using Multi-layer Internet Overlays
1 Typically, individual DDOS solutions trade service level for security, resulting in overall decreased service performance. Further, each single DDOS solution presents a target fo...
Joseph D. Touch, Gregory G. Finn, Yu-Shun Wang, La...
DSN
2003
IEEE
15 years 12 months ago
N-Way Fail-Over Infrastructure for Reliable Servers and Routers
Maintaining the availability of critical servers and routers is an important concern for many organizations. At the lowest level, IP addresses represent the global namespace by wh...
Yair Amir, Ryan Caudy, Ashima Munjal, Theo Schloss...
185
Voted
DSN
2003
IEEE
15 years 12 months ago
From Crash Tolerance to Authenticated Byzantine Tolerance: A Structured Approach, the Cost and Benefits
Many fault-tolerant group communication middleware systems have been implemented assuming crash failure semantics. While this assumption is not unreasonable, it becomes hard to ju...
Dimane Mpoeleng, Paul D. Ezhilchelvan, Neil A. Spe...