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» The many levels of CSCL
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IPPS
2000
IEEE
15 years 11 months ago
Monotonic Counters: A New Mechanism for Thread Synchronization
Only a handful of fundamental mechanisms for synchronizing the access of concurrent threads to shared memory are widely implemented and used. These include locks, condition variab...
John Thornley, K. Mani Chandy
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 11 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
HICSS
1998
IEEE
112views Biometrics» more  HICSS 1998»
15 years 11 months ago
The Dynamics of Market Power with Deregulated Electricity Generation Supplies
Deregulated wholesale markets for bulk electricity supplies are likely to deviate from the perfectly competitive ideal in many areas where transmission losses, costs and capacity ...
Richard E. Schuler
SPAA
1998
ACM
15 years 11 months ago
Elimination Forest Guided 2D Sparse LU Factorization
Sparse LU factorization with partial pivoting is important for many scienti c applications and delivering high performance for this problem is di cult on distributed memory machin...
Kai Shen, Xiangmin Jiao, Tao Yang
APCSAC
2007
IEEE
15 years 10 months ago
Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters
Many years of CMOS technology scaling have resulted in increased power densities and higher core temperatures. Power and temperature concerns are now considered to be a primary cha...
Daniel C. Vanderster, Amirali Baniasadi, Nikitas J...