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DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 12 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
15 years 12 months ago
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
Prabhat Mishra, Nikil D. Dutt
ICMCS
2005
IEEE
153views Multimedia» more  ICMCS 2005»
15 years 12 months ago
Improved semantic region labeling based on scene context
Semantic region labeling in outdoor scenes, e.g., identifying sky, grass, foliage, water, and snow, facilitates content-based image retrieval, organization, and enhancement. A maj...
Matthew R. Boutell, Jiebo Luo, Christopher M. Brow...
IPPS
2005
IEEE
15 years 12 months ago
Bootstrapping Free-Space Optical Networks
Title of thesis: BOOTSTRAPPING FREE-SPACE OPTICAL NETWORKS Fang Liu, Master of Science, 2004 Thesis directed by: Professor Uzi Vishkin Department of Electrical and Computer Engine...
Fang Liu, Uzi Vishkin, Stuart Milner
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
15 years 12 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...