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EUROPAR
2001
Springer
15 years 11 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
IV
2000
IEEE
112views Visualization» more  IV 2000»
15 years 11 months ago
Evaluating Visualizations Based on the Performed Task
This paper describes an ongoing project with the goal of designing and implementing a method to evaluate visualizations based on the tasks supported. The method evaluates time to ...
Octavio Juarez Espinosa, Chris Hendrickson, James ...
DATE
2010
IEEE
140views Hardware» more  DATE 2010»
15 years 11 months ago
Construction of dual mode components for reconfiguration aware high-level synthesis
High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area...
George Economakos, Sotirios Xydis, Ioannis Koutras...
DATE
2010
IEEE
145views Hardware» more  DATE 2010»
15 years 11 months ago
Energy-efficient real-time task scheduling with temperature-dependent leakage
Abstract--Leakage power consumption contributes significantly to the overall power dissipation for systems that are manufactured in advanced deep sub-micron technology. Different f...
Chuan-Yue Yang, Jian-Jia Chen, Lothar Thiele, Tei-...
MSS
1999
IEEE
85views Hardware» more  MSS 1999»
15 years 11 months ago
Tape Group Parity Protection
We propose a new method of ensuring the redundant storage of information on tertiary storage, especially tape storage. Conventional methods for redundant data storage on tape incl...
Theodore Johnson, Sunil Prabhakar