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ISCAS
2007
IEEE
135views Hardware» more  ISCAS 2007»
16 years 17 days ago
Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology
Abstract—In the nanometer-scale CMOS technology, the gateoxide thickness has been scaled down to support a higher operating speed under a lower power supply (1xVDD). However, the...
Ming-Dou Ker, Hung-Tai Liao
ESANN
2008
15 years 7 months ago
Petri nets design based on neural networks
Petri net faulty models are useful for reliability analysis and fault diagnosis of discrete event systems. Such models are difficult to work out as long as they must be computed ac...
Edouard Leclercq, Souleiman Ould el Medhi, Dimitri...
IEEECIT
2006
IEEE
16 years 9 days ago
The Partitioning Methodology in Hardware/Software Co-Design Using Extreme Programming: Evaluation through the Lego Robot Project
This paper argues about the partitioning in hardware/software co-design and suggests the methodology applying extreme programming to complement the co-design. This approach, contr...
Heeseo Chae, Dong-hyun Lee, Jiyong Park, Hoh Peter...
ICCD
2005
IEEE
119views Hardware» more  ICCD 2005»
16 years 3 months ago
Deployment of Better Than Worst-Case Design: Solutions and Needs
The advent of nanometer feature sizes in silicon fabrication has triggered a number of new design challenges for computer designers. These challenges include design complexity and...
Todd M. Austin, Valeria Bertacco
DAC
2005
ACM
15 years 8 months ago
Logic soft errors in sub-65nm technologies design and CAD challenges
Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technolog...
Subhasish Mitra, Tanay Karnik, Norbert Seifert, Mi...