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DATE
2010
IEEE
160views Hardware» more  DATE 2010»
15 years 11 months ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...
MSS
2000
IEEE
79views Hardware» more  MSS 2000»
15 years 10 months ago
A Scalable Architecture for Maximizing Concurrency
This paper describes a design that addresses limitations inherent in the initial implementation of the Archive for the Earth Observing Systems (EOS). The design consists of two el...
Jonathan Crawford
DAC
2008
ACM
16 years 7 months ago
Feedback-controlled reliability-aware power management for real-time embedded systems
In recent literature it has been reported that Dynamic Power Management (DPM) may lead to decreased reliability in real-time embedded systems. The ever-shrinking device sizes cont...
Ranjani Sridharan, Nikhil Gupta, Rabi N. Mahapatra
ASPDAC
2008
ACM
103views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Reliability-aware design for nanometer-scale devices
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges...
David Atienza, Giovanni De Micheli, Luca Benini, J...
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
15 years 11 months ago
Reducing pin and area overhead in fault-tolerant FPGA-based designs
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz...