72 search results - page 12 / 15 » The design of a low power asynchronous multiplier |
170
click to vote
ASPDAC
2008
ACM
15 years 8 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
189
click to vote
TVLSI
2010
15 years 22 days ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
185
click to vote
IPPS
2003
IEEE
15 years 11 months ago
2003
IEEE
Clustering is an important characteristic of most sensor applications. In this paper we define COSMOS, the Cluster-based, heterOgeneouS MOdel for Sensor networks. The model assum...
165
click to vote
DAC
2007
ACM
16 years 7 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
152
click to vote
ISLPED
2009
ACM
15 years 10 months ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...