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ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
15 years 11 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
JTAER
2010
173views more  JTAER 2010»
15 years 5 months ago
An Assessment of Design Patterns' Influence on a Java-based E-Commerce Application
Design patterns, acting as recurring solutions to common problems, offer significant benefits such as avoiding unnecessary complexity, and promoting code reuse, maintainability an...
Maria Mouratidou, Vassilios Lourdas, Alexander Cha...
DAC
2009
ACM
16 years 7 months ago
Evaluating design trade-offs in customizable processors
The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly...
Unmesh D. Bordoloi, Huynh Phung Huynh, Samarjit Ch...
163
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DAC
2000
ACM
16 years 7 months ago
Designing systems-on-chip using cores
Leading-edge systems-on-chip (SoC) being designed today could reach 20 Million gates and 0.5 to 1 GHz operating frequency. In order to implement such systems, designers are increa...
Reinaldo A. Bergamaschi, William R. Lee
DAC
2006
ACM
16 years 7 months ago
Shielding against design flaws with field repairable control logic
Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs...
Ilya Wagner, Valeria Bertacco, Todd M. Austin