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ISQED
2009
IEEE
70views Hardware» more  ISQED 2009»
16 years 1 months ago
Place and route considerations for voltage interpolated designs
— Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. It...
Kevin Brownell, Ali Durlov Khan, David Brooks, Gu-...
RECONFIG
2009
IEEE
141views VLSI» more  RECONFIG 2009»
16 years 1 months ago
Enhancing the Productivity of Radio Designers with RapidRadio
—In this paper the RapidRadio framework for signal classification and receiver deployment is discussed. The framework is a productivity enhancing tool that reduces the required ...
Jorge Surís, Adolfo Recio, Peter Athanas
ISMVL
2008
IEEE
134views Hardware» more  ISMVL 2008»
16 years 1 months ago
Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells
Nanoscale multiple-valued logic systems require the development of nanometer scale integrated circuits and components. Due to limits in device physics, new components must be deve...
Theodore W. Manikas, Dale Teeters
ICALT
2003
IEEE
15 years 12 months ago
Designing Multimedia Support for Situated Learning
Situated learning is known to be an effective didactic approach, yet, multimedia systems with built-in support for it are uncommon. We analyze the domain-independent requirements ...
Alexei Tretiakov, Kinshuk, Takako Tretiakov
DATE
2002
IEEE
158views Hardware» more  DATE 2002»
15 years 11 months ago
Congestion Estimation with Buffer Planning in Floorplan Design
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that ...
Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Yo...