This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
A protocol for latency-insensitive design with early evaluation is presented. The protocol is based on a symmetric view of the system in which tokens carrying information move in ...
This paper focuses on designing network processing software for embedded processors. Our design flow CRACC represents an efficient path to implementation based on a modular applic...
Back-pressure is a logical mechanism to control the flow of information on a communication channel of a latency-insensitive system (LIS) while guaranteeing that no packet is lost....
We introduce a constrained mechanism design setting called internal implementation, in which the mechanism designer is explicitly modeled as a player in the game of interest. This...