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DATE
2006
IEEE
151views Hardware» more  DATE 2006»
16 years 26 days ago
An 830mW, 586kbps 1024-bit RSA chip design
This paper presents an RSA hardware design that simultaneously achieves high-performance and lowpower. A bit-oriented, split modular multiplication algorithm and architecture are ...
Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shy...
KBSE
2006
IEEE
16 years 24 days ago
Modularity Analysis of Logical Design Models
Traditional design representations are inadequate for generalized reasoning about modularity in design and its technical and economic implications. We have developed an architectu...
Yuanfang Cai, Kevin J. Sullivan
AUIC
2005
IEEE
16 years 13 days ago
Beautifying Sketching-based Design Tool Content: Issues and Experiences
With the advent of the Tablet PC and stylus-based PDAs, sketching-based user interfaces for design tools have become popular. However, a major challenge with such interfaces is th...
Beryl Plimmer, John C. Grundy
ISCAS
2005
IEEE
158views Hardware» more  ISCAS 2005»
16 years 11 days ago
Designing optimized pipelined global interconnects: algorithms and methodology impact
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
Vidyasagar Nookala, Sachin S. Sapatnekar
DIGRA
2003
Springer
16 years 17 hour ago
Characters in Computer Games: Toward Understanding Interpretation and Design
Interpretation of characters is a fundamental feature of human behavior. Even with limited information available, people will assign personality – even to inanimate objects. Cha...
Petri Lankoski, Satu Heliö, Inger Ekman