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GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
16 years 1 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
16 years 1 months ago
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller ...
Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Ch...
CDVE
2007
Springer
136views Visualization» more  CDVE 2007»
16 years 27 days ago
Cooperative Validation in Distributed Control Systems Design
The team of engineers designing and implementing distributed control system software must communicate within a multidisciplinary environment. One of the main problems is the intera...
Dariusz Choinski, Mieczyslaw Metzger, Witold Nocon...
ICNP
2006
IEEE
16 years 23 days ago
Rigorous Protocol Design in Practice: An Optical Packet-Switch MAC in HOL
— This paper reports on an experiment in network protocol design: we use novel rigorous techniques in the design process of a new protocol, in a close collaboration between syste...
Adam Biltcliffe, Michael Dales, Sam Jansen, Tom Ri...
CODES
2005
IEEE
16 years 10 days ago
An architectural level design methodology for embedded face detection
Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, includin...
Vida Kianzad, Sankalita Saha, Jason Schlessman, Ga...