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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 11 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2010
IEEE
239views Hardware» more  ISCA 2010»
15 years 11 months ago
Sentry: light-weight auxiliary memory access control
Light-weight, flexible access control, which allows software to regulate reads and writes to any granularity of memory region, can help improve the reliability of today’s multi...
Arrvindh Shriraman, Sandhya Dwarkadas
ICPP
2002
IEEE
15 years 11 months ago
Pattern-Based Parallel Programming
The advantages of pattern-based programming have been well-documented in the sequential literature. However patterns have yet to make their way into mainstream parallel computing,...
Steven Bromling, Steve MacDonald, John Anvik, Jona...
ICRA
2002
IEEE
96views Robotics» more  ICRA 2002»
15 years 11 months ago
Mobility Enhancements to the Scout Robot Platform
When a distributed robotic system is assigned to perform reconnaissance or surveillance, restrictions inherent to the design of an individual robot limit the system’s performanc...
Andrew Drenner, Ian T. Burt, Tom Dahlin, Bradley K...
191
Voted
IPPS
2002
IEEE
15 years 11 months ago
Utilization-Based Heuristics for Statically Mapping Real-Time Applications onto the HiPer-D Heterogeneous Computing System
Real-time applications continue to increase in importance as they are employed in various critical areas, such as command and control systems. These applications have traditionall...
Shoukat Ali, Jong-Kook Kim, Yang Yu, Shriram B. Gu...
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