We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
We present a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools p...
The paper is devoted to a brief review of a mathematical theory for the branching variance-reduction technique. The branching technique is an extension of von Neumann’s splittin...
In this work, we provide two heuristic algorithms for the matrix bandwidth reduction problem. The first is a genetic algorithm and the second uses node label adjustments. Experime...
This paper describes an algorithm to calculate near-optimal minimum time trajectories for four wheeled omnidirectional vehicles, which can be used as part of a high-level path pla...