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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
DATE
2002
IEEE
86views Hardware» more  DATE 2002»
15 years 11 months ago
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems
By using a macro/micro state model we show how assumptions on the resolution of logical and physical timing of computation in computer systems has resulted in design methodologies...
JoAnn M. Paul, Donald E. Thomas
USENIX
2008
15 years 8 months ago
A Multi-Site Virtual Cluster System for Wide Area Networks
A virtual cluster is a promising technology for reducing management costs and improving capacity utilization in datacenters and computer centers. However, recent cluster virtualiz...
Takahiro Hirofuchi, Takeshi Yokoi, Tadashi Ebara, ...
FGCS
2010
84views more  FGCS 2010»
15 years 5 months ago
System-level virtualization research at Oak Ridge National Laboratory
System-level virtualization is today enjoying a rebirth, after first gaining popularity in the 1970s as a technique to effectively share what were then considered large computin...
Stephen L. Scott, Geoffroy Vallée, Thomas N...
VR
2000
IEEE
163views Virtual Reality» more  VR 2000»
15 years 10 months ago
Visuo-Haptic Display Using Head-mounted Projector
This paper proposes a novel ‘Visuo-Haptic Display’ using a Head-Mounted Projector (HMP) with X’tal Vision optics. Our goal is to develop the device which enables an observer...
Masahiko Inami, Naoki Kawakami, Dairoku Sekiguchi,...