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» The Underlying Logic of Hoare Logic
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FSEN
2009
Springer
15 years 10 months ago
Executable Interface Specifications for Testing Asynchronous Creol Components
We propose and explore a formal approach for black-box testing asynchronously communicating components in open environments. Asynchronicity poses a challenge for validating and tes...
Immo Grabe, Marcel Kyas, Martin Steffen, Arild B. ...
ATVA
2004
Springer
138views Hardware» more  ATVA 2004»
15 years 10 months ago
Providing Automated Verification in HOL Using MDGs
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
Tarek Mhamdi, Sofiène Tahar
ATVA
2006
Springer
112views Hardware» more  ATVA 2006»
15 years 10 months ago
Synthesis for Probabilistic Environments
In synthesis we construct finite state systems from temporal specifications. While this problem is well understood in the classical setting of non-probabilistic synthesis, this pap...
Sven Schewe
DATE
2004
IEEE
144views Hardware» more  DATE 2004»
15 years 10 months ago
Smaller Two-Qubit Circuits for Quantum Communication and Computation
We show how to implement an arbitrary two-qubit unitary operation using any of several quantum gate libraries with small a priori upper bounds on gate counts. In analogy to librar...
Vivek V. Shende, Igor L. Markov, Stephen S. Bulloc...
DATE
2004
IEEE
97views Hardware» more  DATE 2004»
15 years 10 months ago
A Formal Verification Methodology for Checking Data Integrity
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
Yasushi Umezawa, Takeshi Shimizu