Sciweavers

1536 search results - page 223 / 308
» The Underlying Logic of Hoare Logic
Sort
View
ER
2004
Springer
161views Database» more  ER 2004»
15 years 11 months ago
Towards a Statistically Semantic Web
The envisioned Semantic Web aims to provide richly annotated and explicitly structured Web pages in XML, RDF, or description logics, based upon underlying ontologies and thesauri. ...
Gerhard Weikum, Jens Graupmann, Ralf Schenkel, Mar...
ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
15 years 10 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 10 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
15 years 10 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
CAV
1998
Springer
175views Hardware» more  CAV 1998»
15 years 10 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore