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» The Underlying Logic of Hoare Logic
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VTS
2002
IEEE
101views Hardware» more  VTS 2002»
15 years 11 months ago
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
Shi-Yu Huang
DEON
2010
Springer
15 years 11 months ago
Relevance, Derogation and Permission
Abstract. We show that a recently developed theory of positive permission based on the notion of derogation is hampered by a triviality result that indicates a problem with the und...
Audun Stolpe
IPPS
2000
IEEE
15 years 10 months ago
Declarative Concurrency in Java
We propose a high-level language based on rst order logic for expressing synchronization in concurrent object-oriented programs. The language allows the programmer to declaratively...
Rafael Ramirez, Andrew E. Santosa
APN
2000
Springer
15 years 10 months ago
Pre- and Post-agglomerations for LTL Model Checking
One of the most efficient analysis technique is to reduce an original model into a simpler one such that the reduced model has the same properties than the original one. G. Berthel...
Denis Poitrenaud, Jean-François Pradat-Peyr...
AGP
1999
IEEE
15 years 10 months ago
The Relative Complement Problem for Higher-Order Patterns
We address the problem of complementing higher-order patterns without repetitions of free variables. Differently from the first-order case, the complement of a pattern cannot, in ...
Alberto Momigliano, Frank Pfenning