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» The Underlying Logic of Hoare Logic
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DATE
2010
IEEE
104views Hardware» more  DATE 2010»
15 years 11 months ago
Large-scale Boolean matching
— We propose a methodology for Boolean matching under permutations of inputs and outputs (PP-equivalence checking problem) — a key step in incremental logic design that identif...
Hadi Katebi, Igor L. Markov
EURODAC
1990
IEEE
102views VHDL» more  EURODAC 1990»
15 years 10 months ago
Tools and devices supporting the pseudo-exhaustive test
: In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, inst...
Sybille Hellebrand, Hans-Joachim Wunderlich
ICLP
2007
Springer
15 years 10 months ago
Computing Fuzzy Answer Sets Using dlvhex
Fuzzy answer set programming has been introduced as a framework that successfully combines the concepts of answer set programming and fuzzy logic. In this paper, we show how the fu...
Davy Van Nieuwenborgh, Martine De Cock, Dirk Verme...
CONCUR
2006
Springer
15 years 10 months ago
Liveness, Fairness and Impossible Futures
Impossible futures equivalence is the semantic equivalence on labelled transition systems that identifies systems iff they have the same "AGEF" properties: temporal logic...
Rob J. van Glabbeek, Marc Voorhoeve
FORMATS
2010
Springer
15 years 4 months ago
From Mtl to Deterministic Timed Automata
Abstract. In this paper we propose a novel technique for constructing timed automata from properties expressed in the logic MTL, under bounded-variability assumptions. We handle fu...
Dejan Nickovic, Nir Piterman