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» The Underlying Logic of Hoare Logic
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IAJIT
2010
84views more  IAJIT 2010»
15 years 4 months ago
A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs
: A test procedure for testing mainly the boundary scan cells, and testing partially the test access port controller in programmable logic devices, and field programmable gate arra...
Bashar Al-Khalifa
KR
2000
Springer
15 years 10 months ago
Finding Admissible and Preferred Arguments Can be Very Hard
Bondarenko et al. have recently proposed an extension of the argumentation-theoretic semantics of admissible and preferred arguments, originally proposed for logic programming onl...
Yannis Dimopoulos, Bernhard Nebel, Francesca Toni
VTS
1995
IEEE
100views Hardware» more  VTS 1995»
15 years 10 months ago
Transformed pseudo-random patterns for BIST
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
Nur A. Touba, Edward J. McCluskey
IJCAI
2007
15 years 7 months ago
Tractable Temporal Reasoning
Temporal reasoning is widely used within both Computer Science and A.I. However, the underlying complexity of temporal proof in discrete temporal logics has led to the use of simp...
Clare Dixon, Michael Fisher, Boris Konev
RR
2010
Springer
15 years 4 months ago
Defeasibility in Answer Set Programs via Argumentation Theories
Defeasible reasoning has been studied extensively in the last two decades and many different and dissimilar approaches are currently on the table. This multitude of ideas has made...
Hui Wan, Michael Kifer, Benjamin N. Grosof