1536 search results - page 125 / 308 » The Underlying Logic of Hoare Logic |
189
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
198
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ICST
2009
IEEE
15 years 4 months ago
2009
IEEE
This paper studies the problem of model-based testing of real-time systems that are only partially observable. We model the System Under Test (SUT) using Timed Game Automata (TGA)...
178
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DAC
2003
ACM
16 years 7 months ago
2003
ACM
This paper presents a novel partial assignment technique (PAT) that decides which tasks should be assigned to the same resource without explicitly defining assignment of these tas...
168
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ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...
171
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...