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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
16 years 17 days ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
ISCAS
2006
IEEE
90views Hardware» more  ISCAS 2006»
16 years 17 days ago
Phase measurement and adjustment of digital signals using random sampling technique
—This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
16 years 17 days ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
SP
2006
IEEE
132views Security Privacy» more  SP 2006»
16 years 17 days ago
Towards Automatic Generation of Vulnerability-Based Signatures
In this paper we explore the problem of creating vulnerability signatures. A vulnerability signature matches all exploits of a given vulnerability, even polymorphic or metamorphic...
David Brumley, James Newsome, Dawn Xiaodong Song, ...
TRIDENTCOM
2006
IEEE
16 years 17 days ago
Emulation versus simulation: A case study of TCP-targeted denial of service attacks
—In this paper, we investigate the applicability of simulation and emulation for denial of service (DoS) attack experimentation. As a case study, we consider low-rate TCP-targete...
Roman Chertov, Sonia Fahmy, Ness B. Shroff
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