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» The Timely Computing Base Model and Architecture
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DAC
2004
ACM
16 years 7 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
HPCA
2007
IEEE
16 years 6 months ago
HARD: Hardware-Assisted Lockset-based Race Detection
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
Pin Zhou, Radu Teodorescu, Yuanyuan Zhou
HPCA
2005
IEEE
16 years 6 months ago
Unbounded Transactional Memory
Hardware transactional memory should support unbounded transactions: transactions of arbitrary size and duration. We describe a hardware implementation of unbounded transactional ...
C. Scott Ananian, Krste Asanovic, Bradley C. Kuszm...
CLUSTER
2004
IEEE
15 years 10 months ago
Rolls: modifying a standard system installer to support user-customizable cluster frontend appliances
The Rocks toolkit [9], [7], [10] uses a graph-based framework to describe the configuration of all node types (termed appliances) that make up a complete cluster. With hundreds of...
Greg Bruno, Mason J. Katz, Federico D. Sacerdoti, ...
DAC
2005
ACM
15 years 8 months ago
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
Chong Zhao, Yi Zhao, Sujit Dey