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» The Timely Computing Base Model and Architecture
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DAC
2003
ACM
16 years 7 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
DAC
2005
ACM
16 years 7 months ago
Diffusion-based placement migration
Placement migration is the movement of cells within an existing placement to address a variety of post-placement design closure issues, such as timing, routing congestion, signal ...
Haoxing Ren, David Zhigang Pan, Charles J. Alpert,...
DAC
2006
ACM
16 years 7 months ago
FLAW: FPGA lifetime awareness
Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vul...
Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie,...
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
16 years 7 months ago
Impact of NBTI on FPGAs
Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS...
Krishnan Ramakrishnan, S. Suresh, Narayanan Vijayk...
ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
16 years 18 days ago
Energy savings through embedded processing on disk system
Abstract— Many of today’s data-intensive applications manipulate disk-resident data sets. As a result, their overall behavior is tightly coupled with their disk performance. Un...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, F...