4679 search results - page 592 / 936 » The Timely Computing Base Model and Architecture |
172
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IPPS
2003
IEEE
15 years 12 months ago
2003
IEEE
Widespread adaptation of shared memory programming for High Performance Computing has been inhibited by a lack of standardization and the resulting portability problems between pl...
169
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JUCS
2006
15 years 6 months ago
2006
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
172
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ICN
2005
Springer
16 years 6 days ago
2005
Springer
It is shown that the de Bruijn graph (dBG) can be used as an architecture for interconnection networks and a suitable structure for parallel computation. Recent works have classiï¬...
161
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Poor performance of HW/SW cosimulation is mainly caused by synchronization requirement between component simulators. Virtual synchronization technique was proposed to remove the n...
171
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ISCAS
2007
IEEE
16 years 1 months ago
2007
IEEE
- This paper aims at discussing the implementation of simulation systems for SNN based on analog computation cores (neuromimetic ICs). Such systems are an alternative to completely...