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NECO
2008
108views more  NECO 2008»
15 years 6 months ago
Optimization of Decision Making in Multilayer Networks: The Role of Locus Coeruleus
Previous theoretical work has shown that a single layer neural network can implement the optimal decision process for simple, two alternative forced choice (2AFC) tasks. However, ...
Eric Shea-Brown, Mark S. Gilzenrat, Jonathan D. Co...
SIGSOFT
1998
ACM
15 years 11 months ago
Reasoning about Implicit Invocation
Implicit invocation SN92, GN91] has become an important architectural style for large-scale system design and evolution. This paper addresses the lack of speci cation and veri cat...
David Garlan, Somesh Jha, David Notkin
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
15 years 11 months ago
A Language for Describing Predictors and Its Application to Automatic Synthesis
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
Joel S. Emer, Nicholas C. Gloy
DAC
2003
ACM
16 years 7 months ago
A tool for describing and evaluating hierarchical real-time bus scheduling policies
We present a tool suite for building, simulating, and analyzing the results of hierarchical descriptions of the scheduling policy for modules sharing a bus in real-time applicatio...
Trevor Meyerowitz, Claudio Pinello, Alberto L. San...
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
16 years 1 days ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...