Sciweavers

4679 search results - page 242 / 936
» The Timely Computing Base Model and Architecture
Sort
View
DAC
1999
ACM
15 years 11 months ago
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar...
ICDE
2008
IEEE
119views Database» more  ICDE 2008»
16 years 8 months ago
Toward Simulation-Based Optimization in Data Stream Management Systems
Abstract-- Our demonstration introduces a novel system architecture which massively facilitates optimization in data stream management systems (DSMS). The basic idea is to decouple...
Bernhard Seeger, Christoph Heinz, Jürgen Kr&a...
DAC
2000
ACM
15 years 11 months ago
Passive model order reduction of multiport distributed interconnects
Signal integrity analysis has become imperative for high-speed designs. In this paper, we present a new technique to advance Krylov-space based passive model-reduction algorithms ...
Emad Gad, Anestis Dounavis, Michel S. Nakhla, Rama...
WMPI
2004
ACM
15 years 12 months ago
Compiler-optimized usage of partitioned memories
In order to meet the requirements concerning both performance and energy consumption in embedded systems, new memory architectures are being introduced. Beside the well-known use o...
Lars Wehmeyer, Urs Helmig, Peter Marwedel
DAC
2002
ACM
16 years 7 months ago
Transformation based communication and clock domain refinement for system design
The ForSyDe methodology has been developed for system level design. In this paper we present formal transformation methods for the refinement of an abstract and formal system mode...
Ingo Sander, Axel Jantsch