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AICCSA
2001
IEEE
112views Hardware» more  AICCSA 2001»
15 years 10 months ago
Implementation of DDARC: Software Architecture for Debugging Distributed Programs
Debugging and testing is a larger part of the effort spent in a software development cycle. Debugging a program is time consuming and is a continuous cycle of code modification an...
Sushma Rai, D. Sampath, Srivathsa N. S.
ICPR
2008
IEEE
16 years 1 months ago
Computer-aided grading of lymphangioleiomyomatosis (LAM) using HRCT
Lymphangioleiomyomatosis (LAM) is a multisystem disorder associated with proliferation of smooth muscle-like cells, which leads to destruction of lung parenchyma. Subjective gradi...
Jianhua Yao, Nilo Avila, Andrew Dwyer, Angelo M. T...
DFT
1998
IEEE
88views VLSI» more  DFT 1998»
15 years 11 months ago
Characterization of CMOS Defects using Transient Signal Analysis
We present the results of hardware experiments designed to determine the relative contribution of CMOS coupling mechanisms to off-path signal variations caused by common types of ...
James F. Plusquellic, Donald M. Chiarulli, Steven ...
ERSA
2006
147views Hardware» more  ERSA 2006»
15 years 8 months ago
Code Partitioning for Reconfigurable High-Performance Computing: A Case Study
In this case study, various ways to partition a code between the microprocessor and FPGA are examined. Discrete image convolution operation with separable kernel is used as the ca...
Volodymyr V. Kindratenko
179
Voted
ICCAD
2004
IEEE
127views Hardware» more  ICCAD 2004»
16 years 3 months ago
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...