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DATE
1999
IEEE
194views Hardware» more  DATE 1999»
15 years 11 months ago
Algorithms for Solving Boolean Satisfiability in Combinational Circuits
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
Luís Guerra e Silva, Luis Miguel Silveira, ...
LREC
2008
87views Education» more  LREC 2008»
15 years 8 months ago
Is this NE tagger getting old?
This paper focuses on the influence of changing the text time frame on the performance of a named entity tagger. We followed a twofold approach to investigate this subject: on the...
Cristina Mota, Ralph Grishman
AAAI
1994
15 years 8 months ago
Tractable Planning with State Variables by Exploiting Structural Restrictions
So far, tractable planning problems reported in the literature have been defined by syntactical restrictions. To better exploit the inherent structure in problems, however, it is ...
Peter Jonsson, Christer Bäckström
WISE
2009
Springer
16 years 1 months ago
Recommending Improvements to Web Applications Using Quality-Driven Heuristic Search
Planning out maintenance tasks to increase the quality of Web applications can be difficult for a manager. First, it is hard to evaluate the precise effect of a task on quality. S...
Stéphane Vaucher, Samuel Boclinville, Houar...
DFT
2005
IEEE
92views VLSI» more  DFT 2005»
16 years 11 days ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...