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ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
ECRTS
2004
IEEE
15 years 10 months ago
A Variable Rate Execution Model
We present a task model for adaptive real-time tasks in which a task's execution rate requirements are allowed to change at any time. The model, variable rate execution (VRE)...
Steve Goddard, Xin Liu
ICANN
2010
Springer
15 years 7 months ago
Model of the Hippocampal Learning of Spatio-temporal Sequences
We propose a model of the hippocampus aimed at learning the timed association between subsequent sensory events. The properties of the neural network allow it to learn and predict ...
Julien Hirel, Philippe Gaussier, Mathias Quoy
SPAA
2000
ACM
15 years 11 months ago
An experimental study of a simple, distributed edge coloring algorithm
We conduct an experimental analysis of a distributed, randomized algorithm for edge coloring graphs. The algorithm is extremely simple, yet, according to the probabilistic analysi...
Madhav V. Marathe, Alessandro Panconesi, Larry D. ...
ITC
1998
IEEE
59views Hardware» more  ITC 1998»
15 years 11 months ago
Stimulus generation for built-in self-test of charge-pump phase-locked loops
Abstract - This paper addresses the issue of the stimulation of charge-pump phase-locked loops for built-in selftest applications. It is shown that three nodes of the PLL qualify f...
Benoît R. Veillette, Gordon W. Roberts