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ATS
2003
IEEE
98views Hardware» more  ATS 2003»
15 years 12 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
DATE
2006
IEEE
102views Hardware» more  DATE 2006»
16 years 21 days ago
Pseudorandom functional BIST for linear and nonlinear MEMS
Pseudorandom test techniques are widely used for measuring the impulse response (IR) for linear devices and Volterra kernels for nonlinear devices, especially in the acoustics dom...
Achraf Dhayni, Salvador Mir, Libor Rufer, Ahc&egra...
IOLTS
2002
IEEE
99views Hardware» more  IOLTS 2002»
15 years 11 months ago
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuit...
Davide Appello, Alessandra Fudoli, Vincenzo Tancor...
151
Voted
DATE
1999
IEEE
80views Hardware» more  DATE 1999»
15 years 11 months ago
Symmetric Transparent BIST for RAMs
The paper introduces the new concept of symmetric transparent BIST for RAMs. This concept allows to skip the signature prediction phase of conventional transparent BIST approaches...
Sybille Hellebrand, Hans-Joachim Wunderlich, Vyach...
FSTTCS
2009
Springer
16 years 1 months ago
The Power of Depth 2 Circuits over Algebras
We study the problem of polynomial identity testing (PIT) for depth 2 arithmetic circuits over matrix algebra. We show that identity testing of depth 3 (ΣΠΣ) arithmetic circuit...
Chandan Saha, Ramprasad Saptharishi, Nitin Saxena