Process variations cause different behavior of timingdependent effects across different chips. In this work, we analyze one example of timing-dependent effects, crosscoupling ...
We introduce a novel global constraint for the total weighted completion time of activities on a single unary capacity resource. For propagating the constraint, we propose an O(n4...
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
Abstract. In this paper, we investigate two novel indexing schemes called DHS and D-HS+PSR(II) designed for use in case-based reasoning systems. D-HS is based on a matrix of cases ...
We introduce a novel global constraint for the total weighted completion time of activities on a single unary capacity resource. For propagating the constraint, an O(n4 ) algorithm...