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IEEEPACT
2003
IEEE
16 years 4 days ago
Design Trade-Offs in High-Throughput Coherence Controllers
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...
Anthony-Trung Nguyen, Josep Torrellas
ISPASS
2003
IEEE
16 years 4 days ago
Accelerating private-key cryptography via multithreading on symmetric multiprocessors
Achieving high performance in cryptographic processing is important due to the increasing connectivity among today’s computers. Despite steady improvements in microprocessor and...
Praveen Dongara, T. N. Vijaykumar
187
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MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
16 years 4 days ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
226
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MSS
2003
IEEE
151views Hardware» more  MSS 2003»
16 years 4 days ago
Accurate Modeling of Cache Replacement Policies in a Data Grid
Caching techniques have been used to improve the performance gap of storage hierarchies in computing systems. In data intensive applications that access large data files over wid...
Ekow J. Otoo, Arie Shoshani
P2P
2003
IEEE
130views Communications» more  P2P 2003»
16 years 4 days ago
Peer-to-Peer Wireless LAN Consortia: Economic Modeling and Architecture
Abstract—In this paper we explore the incentive and architectural issues that arise in Consortia of Peer-to-Peer Wireless Local Area Networks. A P2P WLAN Consortium (PWC) is a co...
Panayotis Antoniadis, Costas Courcoubetis, Elias C...
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