4213 search results - page 574 / 843 » The Tau Parallel Performance System |
159
click to vote
EDBT
2010
ACM
15 years 10 months ago
2010
ACM
Suffix trees are indexing structures that enhance the performance of numerous string processing algorithms. In this paper, we propose cache-conscious suffix tree construction algo...
184
click to vote
ISCA
2008
IEEE
16 years 1 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
150
click to vote
IEEEPACT
2007
IEEE
16 years 1 months ago
2007
IEEE
We present a detailed characterization of instruction cache performance for IBM’s J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks o...
183
click to vote
HOTI
2005
IEEE
16 years 8 days ago
2005
IEEE
Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of ...
141
click to vote
CISIS
2010
IEEE
15 years 12 months ago
2010
IEEE
Abstract—Program performance optimisations, feedbackdirected iterative compilation and auto-tuning systems [1] all assume a fixed estimation of execution time given a fixed inp...