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» The Structure and Performance of Interpreters
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GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
16 years 5 days ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ICDCS
2005
IEEE
16 years 5 days ago
DISC: Dynamic Interleaved Segment Caching for Interactive Streaming
Streaming media objects have become widely used on the Internet, and the demand of interactive requests to these objects has increased dramatically. Typical interactive requests i...
Lei Guo, Songqing Chen, Zhen Xiao, Xiaodong Zhang
IEEEPACT
2005
IEEE
16 years 5 days ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
WACV
2005
IEEE
16 years 4 days ago
Integrating Range and Texture Information for 3D Face Recognition
The performance of face recognition systems that use two-dimensional images depends on consistent conditions w.r.t. lighting, pose, and facial appearance. We are developing a face...
Xiaoguang Lu, Anil K. Jain
ISLPED
2005
ACM
98views Hardware» more  ISLPED 2005»
16 years 4 days ago
Synonymous address compaction for energy reduction in data TLB
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, M...
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