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ASYNC
2000
IEEE
86views Hardware» more  ASYNC 2000»
15 years 11 months ago
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths
This paper introduces several new asynchronous pipeline designs which offer high throughput as well as low latency. The designs target dynamic datapaths, both dualrail as well as ...
Montek Singh, Steven M. Nowick
DATE
2000
IEEE
130views Hardware» more  DATE 2000»
15 years 11 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
DATE
2000
IEEE
124views Hardware» more  DATE 2000»
15 years 11 months ago
On the Generation of Multiplexer Circuits for Pass Transistor Logic
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
Christoph Scholl, Bernd Becker
DCC
2000
IEEE
15 years 11 months ago
Iterative Source/Channel-Decoding Using Reversible Variable Length Codes
In this paper we describe a trellis representation of variable length coded data which is capable of being used for bit-level or symbol-level maximum a posteriori (MAP) decoding o...
Rainer Bauer, Joachim Hagenauer
ICC
2000
IEEE
15 years 11 months ago
Reduced-State BCJR-Type Algorithms
—In this paper, we propose a technique to reduce the number of trellis states in BCJR-type algorithms, i.e., algorithms with a structure similar to that of the well-known algorit...
Giulio Colavolpe, Gian Luigi Ferrari, Riccardo Rah...
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