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EUROMICRO
2007
IEEE
16 years 1 months ago
Partial Verification of Software Components: Heuristics for Environment Construction
Code model checking of software components suffers from the well-known problem of state explosion when applied to highly parallel components, despite the fact that a single compon...
Pavel Parizek, Frantisek Plasil
VISUALIZATION
2005
IEEE
16 years 13 days ago
The Visible Radio: Process Visualization of a Software-Defined Radio
In this case study, a data-oriented approach is used to visualize a complex digital signal processing pipeline. The pipeline implements a Frequency Modulated (FM) Software-Defined...
Matthew Hall, Alex Betts, Donna Cox, David Pointer...
ISSS
2002
IEEE
148views Hardware» more  ISSS 2002»
15 years 11 months ago
A Case Study of Hardware and Software Synthesis in ForSyDe
ForSyDe (FORmal SYstem DEsign) is a methodology which addresses the design of SoC applications which may contain control as well as data flow dominated parts. Starting with a for...
Ingo Sander, Axel Jantsch, Zhonghai Lu
LCTRTS
1999
Springer
15 years 11 months ago
A Software Synthesis Tool for Distributed Embedded System Design
We present a design tool for automated synthesis of embedded systems on distributed COTS-based platforms. Our synthesis tool consists of (1) a graphical user interface for input o...
Dong-In Kang, Richard Gerber, Leana Golubchik, Jef...
ICSE
2007
IEEE-ACM
16 years 7 months ago
UML/Analyzer: A Tool for the Instant Consistency Checking of UML Models
Large design models contain tens of thousands of model elements. Designers easily get overwhelmed maintaining the consistency of such design models over time. Not only is it hard ...
Alexander Egyed