In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylve...
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
A model has been developed to study the global complex dynamics of a series of blackouts in power transmission systems [1, 2]. This model has included a simple level of self-organ...
Benjamin A. Carreras, Vickie E. Lynch, Ian Dobson,...
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
The authors present a multiplication algorithm for low power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual...