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» The Size of Power Automata
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ASPDAC
2007
ACM
131views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...
Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen
ADHOC
2005
176views more  ADHOC 2005»
15 years 6 months ago
A survey of Mobile IP in cellular and Mobile Ad-Hoc Network environments
The Internet has become ubiquitous and there has been tremendous growth in wireless communications in recent years. Many wireless communication techniques are commercially availab...
Tin Yu Wu, Ching-Yang Huang, Han-Chieh Chao
FPGA
2006
ACM
224views FPGA» more  FPGA 2006»
15 years 10 months ago
Flexible implementation of genetic algorithms on FPGAs
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shiba...
CLUSTER
2009
IEEE
16 years 1 months ago
MDCSim: A multi-tier data center simulation, platform
Abstract—Performance and power issues are becoming increasingly important in the design of large cluster based multitier data centers for supporting a multitude of services. Desi...
Seung-Hwan Lim, Bikash Sharma, Gunwoo Nam, Eun-Kyo...
NOCS
2008
IEEE
16 years 1 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...