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VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
16 years 7 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
RECOMB
2005
Springer
16 years 7 months ago
Alignment of Optical Maps
We introduce a new scoring method for calculation of alignments of optical maps. Missing cuts, false cuts, and sizing errors present in optical maps are addressed by our alignment...
Anton Valouev, Lei Li, Yu-Chi Liu, David C. Schwar...
ICRA
2007
IEEE
160views Robotics» more  ICRA 2007»
16 years 28 days ago
Morphing Bus: A rapid deployment computing architecture for high performance, resource-constrained robots
— For certain applications, field robotic systems require small size for cost, weight, access, stealth or other reasons. Small size results in constraints on critical resources s...
Colin D'Souza, Byung Hwa Kim, Richard M. Voyles
SPAA
2005
ACM
16 years 6 days ago
Parallelizing time with polynomial circuits
We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing ...
Ryan Williams
ISCA
2003
IEEE
212views Hardware» more  ISCA 2003»
15 years 12 months ago
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels
Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM...
Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi...