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» The Size of Power Automata
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CODES
2006
IEEE
16 years 21 days ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
15 years 12 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...
CVPR
2007
IEEE
16 years 8 months ago
Toward A Discriminative Codebook: Codeword Selection across Multi-resolution
In patch-based object recognition, there are two important issues on the codebook generation: (1) resolution: a coarse codebook lacks sufficient discriminative power, and an over-...
Lei Wang
DAC
2007
ACM
16 years 7 months ago
On-The-Fly Resolve Trace Minimization
The ability of modern SAT solvers to produce proofs of unsatisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve t...
Ohad Shacham, Karen Yorav
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 7 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar